1. Field of the Invention
The present invention is related to a wire load estimating method and a wire load estimating computer program product for estimating wire loads between instances such as cells, macro blocks and synthesized blocks and a repeater cell inserting method and a repeater cell inserting computer program product for determining the location of a repeater cell to be inserted on a long wire.
2. Description of the Related Art
Along with the advent of the miniaturization of LSIs, the signal delay originating from wiring delays, rather than originating from gate delays, become a serious problem. Because of this, it is significantly important to estimate wire loads (the wire resistance and the wire capacitance) with a higher degree of accuracy for the purpose of executing logic simulation, timing simulation and so forth.
In accordance with a conventional technique, the wire resistance values and the wire capacitance values are calculated in accordance with the following procedures.
(Procedure 1-1) A netlist is input to a place and route tool, followed by automatically routing and placing parts and wires.
(Procedure 1-2) The number of connection points, the wire capacitance value and the wire resistance value are obtained for each net by the use of the layout as generated.
(Procedure 1-3) The numbers of connection points, the wire capacitance values and the wire resistance values are statistically processed in order to calculate the wire capacitance value and the wire resistance value corresponding to each of the numbers of connection points. The result is stored in the storage area of a computer system in the form of a table.
These preliminary procedures are repeated for generating a table of the wire capacitance value and the wire resistance value corresponding to each of the numbers of connection points in accordance with the above procedures 1-1 to 1-3.
FIG. 1 is one example of such tables. The wire capacitance value and the wire resistance value of each net are calculated with reference to these tables.
(Procedure 2-1) The information about the number of connection points for each net is obtained by the use of the netlist. (Procedure 2-2) In usual cases, the netlist is hierarchically described so that the netlist is flattened in advance of calculating the information about the numbers of connection points.
(Procedure 2-1) The wire capacitance value and the wire resistance value of each net are calculated with reference to the above table on the basis of the information about the number of connection points as calculated.
The number of connection points, the wire capacitance value and the wire resistance value are obtained for each net of the netlist in accordance with the above procedures 2-1 to 2-2.
In the case that a wire is eventually extended for a long length, a repeater cell must be inserted thereto.
As illustrated in FIG. 2, in accordance with the method of the prior art technique, cells are placed in the step S312 after reading the netlist 10; a detailed routing process is conducted in the step S314 for outputting the wire capacitance values and the wire resistance values 316; a repeater cell(s) is inserted with reference to the netlist 10, the wire capacitance value and the wire resistance value in the step S318 followed by outputting a netlist 320 with a repeater cell(s); the differential layout is obtained by comparing the netlist 320 with a repeater cell(s) and the original netlist 10 in the step S322; cells are re-placed with fine adjustment of the cell locations in the periphery in accordance with the differential layout in the step S324; the wiring layout is re-routed in the step S326; the sizes of gates are adjusted in accordance with the wire loads which are modified after re-routing the wiring layout in the step S328; and the cells are re-placed and re-routed in accordance with the netlist after changing the sizes of gates in the step S330 in the course of the Engineering Change Order (ECO) process in order to output a layout 332.
The operation of the prior art technique is as follows. First, the placement of cells and the detailed routing process are conducted by means of an automatic place and route tool in order to output the wire capacitance values and the wire resistance values. A repeater cell is inserted to the path of a signal accompanied with a large capacitance with reference to the wire capacitance values as obtained. Re-placement of the cells and the re-routing of connection points is then conducted with respect to only the modified areas which are determined by comparing the netlist after inserting a repeater cell(s) and the original netlist before inserting a repeater cell(s). The re-placement of the cells and the re-routing of connection points is conducted in order to retain as much as possible of the original layout before inserting a repeater cell(s). The layout of cells and the re-routing of connection points are then adjusted after changing the sizes of gates in accordance with a usual process of circuit design, followed by outputting an adjusted layout.